Search - rs232 vhdl

[SourceCode] VHDL实现RS232串口通信源码

Description: QUARTUS2下VHDL实现串口通信的源码，整个工程分四个模块：顶层，波特率产生模块，发送模块，接受模块。
Platform: | Size: 2464 | Author: lkac13 | Hits:

[VHDL-FPGA-Verilog] async--RS232

Description: async--RS232VERILOG HDL原代码-async-- RS232VERILOG HDL source
Platform: | Size: 3072 | Author: chenxiao | Hits:

[Embeded-SCM Develop] rs232lan

Description: CPLD 9536 程序我自己用的代码. VHDL语言-CPLD 9,536 procedures for my own use code. VHDL
Platform: | Size: 621568 | Author: 罗明 | Hits:

[VHDL-FPGA-Verilog] vhdl_rs232

Description: 使用FPGA透过RS232与PC的作沟通，
Platform: | Size: 3072 | Author: 苏山河 | Hits:

[VHDL-FPGA-Verilog] yibutongxin

Description: 用VHDL编写的串口异步通信的例子，适于RS232、RS422的通信-err
Platform: | Size: 558080 | Author: 王权 | Hits:

[Other Embeded program] RS232

Description: 基于XILINX的内嵌POWERPC的处理器的串行通讯的应用源代码.-XILINX PowerPC-based embedded processor serial communication application source code.
Platform: | Size: 344064 | Author: 王晶 | Hits:

Description: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Platform: | Size: 5120 | Author: 陈想 | Hits:

[VHDL-FPGA-Verilog] cyclic

Description: FPGA的串口通信程序，可接受或者发送数据，通过Rs232口-FPGA serial communication program, acceptable, or send data through the RS232 port
Platform: | Size: 1307648 | Author: xianchunwwang | Hits:

[VHDL-FPGA-Verilog] FPGArealizeRS232

Description: 用FPGA实现RS232通信,此代码是用VHDL语言编写，非常有用的好东东啊-RS232 Communication with FPGA realize that this code is written in VHDL, very useful, good东东啊
Platform: | Size: 48128 | Author: 孙建军 | Hits:

[VHDL-FPGA-Verilog] Verilog_example

Description: 本文件包括多路选择器器建模，译码器实验程序，加法器实验程序，比较器实验程序，计数器建模，I2C接口标准建模源码，串行接口RS232标准建模源码标准，LCM建模源码，时钟６分频源码，串并转化源码。，对于硬件设计初学者来说有一定的参考价值。-This document includes MUX device modeling, experimental procedure decoder, adder experimental procedures, experimental procedures comparators, counters modeling, I2C interface standard modeling source, standard RS232 serial interface modeling source standards, LCM modeling source, clock frequency source 6, and transforming source string. For hardware design beginners have a certain reference value.
Platform: | Size: 1064960 | Author: 朱秋玲 | Hits:

[VHDL-FPGA-Verilog] 232_receiver

Description: Rs232 receiver usage -Rs232 receiver usage
Platform: | Size: 1024 | Author: wei hi | Hits:

[VHDL-FPGA-Verilog] 232_transmitter

Description: Rs232 tramslator usage -Rs232 tramslator usage
Platform: | Size: 1024 | Author: wei hi | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[Com Port] uart(Verilog)

Description: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Platform: | Size: 10240 | Author: 陈强 | Hits:

[Com Port] b13c_environment

Description: rs232控制器，实现rs232的环境设置，verilog编写，所有权归opencores-rs232 controller rs232 to achieve the environmental settings, verilog prepared, owned by opencores
Platform: | Size: 63488 | Author: uknow | Hits:

[Com Port] uart

Description: 基于MAXII的RS232串口通信程序.还有使用VB编写的上位机串口通信软件。-MAXII based on the RS232 serial communication program. There are prepared to use VB PC serial communication software.
Platform: | Size: 199680 | Author: 张勋 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
Platform: | Size: 121856 | Author: pp | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）；并在数据接收区显示接收到的字符。串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Platform: | Size: 730112 | Author: 李华 | Hits:

[Books] ComunicationRealizationBetweenFPGAandSerialInterfa

Description: 杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。 -杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.
Platform: | Size: 92160 | Author: Wuxinmin | Hits:

[VHDL-FPGA-Verilog] RS232

Description: RS232串口驱动，使用alter公司的ep3c芯片-RS232
Platform: | Size: 1629184 | Author: 七夜 | Hits:

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[SourceCode] VHDL实现RS232串口通信源码

[VHDL-FPGA-Verilog] async--RS232

[Embeded-SCM Develop] rs232lan

[VHDL-FPGA-Verilog] vhdl_rs232

[VHDL-FPGA-Verilog] yibutongxin

[Other Embeded program] RS232

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] cyclic

[VHDL-FPGA-Verilog] FPGArealizeRS232

[VHDL-FPGA-Verilog] Verilog_example

[VHDL-FPGA-Verilog] 232_receiver

[VHDL-FPGA-Verilog] 232_transmitter

[VHDL-FPGA-Verilog] UART

[Com Port] uart(Verilog)

[Com Port] b13c_environment

[Com Port] uart

[VHDL-FPGA-Verilog] rs232

[VHDL-FPGA-Verilog] RS232

[Books] ComunicationRealizationBetweenFPGAandSerialInterfa

[VHDL-FPGA-Verilog] RS232

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